Instruction Recycling on a Multiple-Path Processor

نویسندگان

  • Steven Wallace
  • Dean M. Tullsen
  • Brad Calder
چکیده

Processors that can simultaneously execute multiple paths of execution will only exacerbate the fetch bandwidth problem already plaguing conventional processors. On a multiple-path processor, which speculatively executes less likely paths of hard-to-predict branches, the work done along a speculative path is normally discarded if that path is found to be incorrect. Instead, it can be beneficial to keep these instruction traces stored in the processor for possible future

برای دانلود رایگان متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Ac 2011-5: an Instructional Processor Design Using Vhdl and an Fpga

Most modern processors are too complex to be used as an introductory design example. Many digital design courses and texts use hardware description language models of processors, but they are often ad hoc. What is needed is a basic processor with sufficient complexity, that can be modified, programmed, and tested. An instructional processor has been developed for use as a design example in an A...

متن کامل

Exploiting the Prefetching Effect Provided by Executing Mispredicted Load Instructions

As the degree of instruction-level parallelism in superscalar architectures increases, the gap between processor and memory performance continues to grow requiring more aggressive techniques to increase the performance of the memory system. We propose a new technique, which is based on the wrong-path execution of loads far beyond instruction fetch-limiting conditional branches, to exploit more ...

متن کامل

MPS: Miss-Path Scheduling for Multiple-Issue Processors

Many contemporary multiple issue processors employ out-of-order scheduling hardware in the processor pipeline. Such scheduling hardware can yield good performance without relying on compile-time scheduling. The hardware can also schedule around unexpected run-time occurrences such as cache misses. As issue widths increase, however, the complexity of such scheduling hardware increases considerab...

متن کامل

HydraScalar: A Multipath-Capable Simulator

Even sophisticated branch-prediction techniques necessarily suffer some mispredictions, and even relatively small mispredict rates hurt performance substantially in current-generation processors. This suggests the study of multipath execution, in which the processor simultaneously executes code from both the taken and not-taken outcomes of a branch. This paper describes HydraScalar, a simulator...

متن کامل

Miss Path Speculative Scheduling for High Issue Rates

Many contemporary multiple issue processors employ out-of-order scheduling hardware in the processor pipeline. Such scheduling hardware can yield good performance without relying on compile-time scheduling. The hardware can also schedule around unexpected run-time occurrences such as cache misses. As issue widths increase, the complexity of such scheduling hardware increases considerably and ca...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 1999